diff --git a/gpu/src/command_encoder.zig b/gpu/src/command_encoder.zig index 956a07b2..8264d1a7 100644 --- a/gpu/src/command_encoder.zig +++ b/gpu/src/command_encoder.zig @@ -21,8 +21,8 @@ pub const CommandEncoder = *opaque { return Impl.commandEncoderBeginRenderPass(command_encoder, descriptor); } - // Default `offset`: 0 - // Default `size`: `gpu.whole_size` + /// Default `offset`: 0 + /// Default `size`: `gpu.whole_size` pub inline fn clearBuffer(command_encoder: CommandEncoder, buffer: Buffer, offset: u64, size: u64) void { Impl.commandEncoderClearBuffer(command_encoder, buffer, offset, size); } diff --git a/gpu/src/compute_pass_encoder.zig b/gpu/src/compute_pass_encoder.zig index 4ad45595..cfb72910 100644 --- a/gpu/src/compute_pass_encoder.zig +++ b/gpu/src/compute_pass_encoder.zig @@ -12,8 +12,8 @@ pub const ComputePassEncoder = *opaque { Impl.computePassEncoderDispatchIndirect(compute_pass_encoder, indirect_buffer, indirect_offset); } - // Default `workgroup_count_y`: 1 - // Default `workgroup_count_z`: 1 + /// Default `workgroup_count_y`: 1 + /// Default `workgroup_count_z`: 1 pub inline fn dispatchWorkgroups(compute_pass_encoder: ComputePassEncoder, workgroup_count_x: u32, workgroup_count_y: u32, workgroup_count_z: u32) void { Impl.computePassEncoderDispatchWorkgroups(compute_pass_encoder, workgroup_count_x, workgroup_count_y, workgroup_count_z); } @@ -42,8 +42,8 @@ pub const ComputePassEncoder = *opaque { Impl.computePassEncoderPushDebugGroup(compute_pass_encoder, group_label); } - // Default `dynamic_offset_count`: 0 - // Default `dynamic_offsets`: null + /// Default `dynamic_offset_count`: 0 + /// Default `dynamic_offsets`: null pub inline fn setBindGroup(compute_pass_encoder: ComputePassEncoder, group_index: u32, group: BindGroup, dynamic_offset_count: u32, dynamic_offsets: ?[*]const u32) void { Impl.computePassEncoderSetBindGroup(compute_pass_encoder, group_index, group, dynamic_offset_count, dynamic_offsets); }